1. Field of the Invention
The present invention relates to interconnect links, specifically, a method and apparatus for power reduction in receiver circuitry used for an interconnect link.
2. Description of the Related Art
As is well known, input/output (I/O) buses connect different components together in a computer system. One example of an I/O bus is a link, which is a point-to-point interconnect connecting two components (these components can be on the same circuit board or across two different boards). A link could be bi-directional and consists of an out-going direction and an in-coming direction. Likewise, the width of the link is scalable from one bit (a.k.a. serial) to multiple bits in parallel. A single bit is transferred from the source component via a transmitter and received at the destination via a receiver. In the multi-bit parallel links, multiple bits are transferred simultaneously in parallel through multiple transmitter and receiver pairs. The signaling technology can be single-ended or differential.
PCI-express and SCID links are utilized for serial interface communication. For reference, PCI-express is discussed in “PCI-express Base Specification Rev 1.0, Jul. 22, 2002”.
Squelch receivers are used by serial interfaces such as PCI Express to detect an exit from electrical idle initiated by the device on the other side of the link. Electrical idle is a steady state condition where the transmitter and receiver voltages are held constant. Nonetheless, the squelch receivers need to remain powered on when the rest of the receiver circuit is in a low power mode. Consequently, this increases the power consumption for the interconnect link circuitry.